FPGA that doesn’t use a global clock, but rather “message passing” in hardware to achieve synchronization.

http://www.edn.com/index.asp?layout=blogpostPrint&blog_post_id=1040033304
“The tale starts with one of the less popular approaches to asynchronous logic: two-wire signaling with a separate acknowledge wire, also known as three-wire asynchronous logic. (A big hint toward what Achronix architects have been up to appeared in IEEE Computer Society transactions in 2004.) In this system, when a logic gate creates an output, it codes the 1 or 0 on two separate pins. That allows for three active states: 1, 0, and no-signal. The next gate in the net is designed to wait until the no-signal states of all its inputs have turned into unambiguous 1s or 0s before acting. Once the gate has satisfied its hold time, it sends an acknowledge signal back up the net to the sources of the inputs, allowing them to move on to their next state.

In this way an entire logic net is self-timed. Signals propagate through the network limited only by wire delays and the time it takes each logic element to actually do its work. As soon as all of the inputs have arrived at a LUT and it has received Acknowledge signals from all the inputs it fans out to, it will look up the correct output and transfer it to its output pins, and signal the LUTs that created the input signals that they need wait no longer. The effect is similar to a technique known as wave pipelining that allows pipelines to operate without the use of internal latches.”